1. Technical Field
The present invention relates to power semiconductor devices used in electric power converters and the like. Specifically, the invention relates to MOS-type semiconductor devices such as IGBT and a manufacturing method thereof.
2. Background Art
A description will be given of a breakdown withstanding section in a heretofore known power semiconductor device. FIG. 2 is a cross sectional view of a breakdown withstanding section having guard rings in a heretofore known semiconductor device. In FIG. 2, a breakdown withstanding section 200 in a power semiconductor device 300 is usually arranged in a chip edge area surrounding an active section 100 that engages in making a main current flow in a conductive state of the power semiconductor device 300.
Usually, it is often the case that a guard ring structure, wherein a plurality of p-type semiconductor diffusion regions of opposite polarity (abbreviated to p-type regions 31) are arranged so as to form a planar ring pattern in a surface portion of an n-type semiconductor substrate 30, is employed in the breakdown withstanding section 200 in the kind of high breakdown voltage power semiconductor device 300 shown in FIG. 2.
The p-type regions 31 configuring the guard ring structure are formed by selective boron ion implantation from a semiconductor substrate 30 surface and by thermal diffusion. Therefore, a pn-junction portion that constitutes a boundary between the n-type semiconductor substrate 30 and the p-type region 31 (hereinafter referred to as “the boundary-constituting pn-junction portion”) forms a U-shaped cross section with the substrate surface as a terminus portion.
As a result, a curved section 32 indicating an equipotential curve distribution of a depletion layer spreading from the boundary-constituting pn-junction portion when an OFF-voltage is applied is formed following a U-shaped curved portion of the boundary-constituting pn-junction portion. The electric field localization in the curved section 32 is relaxed by the guard ring structure with this kind of configuration, but the electric field relaxation is not always sufficient, and a drop in breakdown voltage may be unavoidable.
Also, in the selective thermal diffusion of impurity atoms into the semiconductor substrate, a diffusion region is formed by the impurity atoms diffusing to expand in the vertical and lateral directions into the semiconductor substrate from an opening area in the semiconductor substrate surface or from an ion-implanted region. As the diffusion region expands not only in the depth direction but also in the lateral directions, the width of the impurity atom spread is greater than that of the opening area at the start of the selective thermal diffusion of the impurity atoms into the semiconductor substrate.
For improving the breakdown voltage and the reliability thereof, a thick oxide film (a field oxide film 33) with a thickness of 5000 angstroms (Å) or more is usually formed on the surface of the breakdown withstanding section 200 of the semiconductor substrate. Furthermore, in some cases, a configuration that makes an electrically conductive polysilicon layer or an electrically conductive film formed on the field oxide film 33 as a field plate 34 that exhibits an electric field relaxation function is adopted.
When an IGBT is considered specifically as the power semiconductor device 300 that includes the breakdown withstanding section 200, the IGBT is brought into an ON-state when a voltage of a predetermined threshold value or higher is applied to a gate electrode in a MOS structure in the active section 100. Surface electron layers, such as an inversion layer (n-channel) induced in a surface portion of a p-type base region of a silicon semiconductor substrate opposing the gate electrode via a gate oxide film and a storage layer induced in a surface portion of an n-type layer, an n-type drift layer, a collector junction, a p-type collector layer, and the like, exist in a current path when the IGBT is in the ON-state. An ON-voltage is obtained by summing up voltage drop values along the ON-state current path.
For reducing the ON-voltage, a shortening of the distance (width) in the electron flow direction in the surface electron layer, that is, a channel shortening, and an increasing of current density by shortening a pitch of a unit cell, which is one unit of a plurality of MOS structures distributed uniformly in a surface portion of the active section, are effective. The shortening of the cell pitch, which increases the cell density in a unit area and reduces the voltage drop value across the surface electron layer in each unit cell, is effective in reducing the ON-voltage.
However, when the carrier (electron, hole) concentration in the drift layer increases, the turnoff loss increases. In other words, there exists a tradeoff relation between the ON-voltage and the turnoff loss. Therefore, it is not sufficient to design the power semiconductor device 300 including the breakdown withstanding section 200, like the IGBT, considering ON-voltage reduction only.
When turning off, a depletion layer expands from the junction on the surface side, and carriers on the surface side are swept out first. That is, the carriers on the surface side are swept out when a bias voltage between a collector and an emitter is relatively low. Because of this, the turnoff loss caused until the carriers on the surface side are swept out, and represented by the product of a voltage and a current, becomes low. Therefore, by considering a structure in which the front-surface-side carrier concentration is higher than the back-surface-side carrier concentration, it is possible to reduce the turnoff loss at the same ON-voltage.
In the newest IGBT's, the carrier concentration in the ON-state of the device is distributed almost flatly, meaning that, by further increasing the carrier concentration on the emitter side, it is possible to further improve the tradeoff relation. In other words, the IGBT's in the present state do not exhibit the IE effect (that is the injection enhancement effect) fully. For further increasing the surface carrier concentration, it is effective to reduce the area of the p-type base region that works as a carrier absorbing layer. With a trench-gate structure mainly employed these days, as it is possible to reduce the p-type base region area at the same channel width as compared with a planar-gate structure, the IE effect is greater.
Regarding the semiconductor devices that exhibit a low ON-voltage, prevent the electric field from localizing, and can increase breakdown voltage, such as that previously described, various means, such as including a guard ring including a protruding semiconductor region in the breakdown withstanding section surface, or a guard ring having a RESURF structure, have already been disclosed (for example, refer to Patent Documents 1 and 2, identified below).
There has been disclosed a document in which is described a device wherein, using a low-cost manufacturing process and with high throughput of non-defective products, the IE effect is large, the ON-voltage is low, and it is possible to obtain a higher breakdown voltage by preventing the electric field from localizing (for example, refer to Patent Document 3, identified below).